I'm currently working on the power line frequency synchronization.
The internal ADC, the AD7190, have a frequency precision of +/-4%.
This frequency deviation causes error in my conversion function.
The software assisted frequency compensation will provide a PLC enabled design.
The selected and tested resampling implementation method uses a 256-points FIR filter with multi-phase Interpolator sin(x)/x and a Kaiser-Bessel derived window. All calculations are done in 64-bit floats.